1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register that includes a plurality of stages where each stage supplies a scan pulse to the next stage and independently to a gate line and thus, preventing the scan pulse applied to the next stage from being distorted, and a method for driving the same.
2. Discussion of the Related Art
Generally, a Liquid Crystal Display (LCD) includes a liquid crystal panel in which a plurality of pixel areas are arranged in the form of a matrix and a drive circuit for driving the liquid crystal panel. A desired image is displayed by controlling an optical transmission rate of the liquid crystal in the liquid crystal panel by using electric fields.
The liquid crystal panel includes a plurality of gate lines and a plurality of data lines intersecting with the gate lines. The gate lines and the data lines are perpendicular to each other at predetermined areas and the predetermined areas serve as pixel areas. The liquid crystal panel includes pixel electrodes for applying electric field to individual pixel areas in conjunction with a common electrode.
Each pixel electrode is connected to the data line via source and drain electrodes of a Thin Film Transistor (TFT) acting as a switching element. The TFT is switched on by a scan pulse applied to a gate electrode of the TFT via the gate line such that a data signal of the data line can charge the pixel electrode.
The drive circuit includes a gate drive for driving the gate lines, a data drive for driving the data lines, a timing controller for providing control signals capable of controlling the gate drives and the gate drives, and a power-supply unit for providing various drive voltages for use in an LCD.
The timing controller controls drive times of the gate drive and the data drive and transmits pixel data signal to the data drive. The power-supply unit steps up or down an input power-supply signal, such that it generates a variety of drive voltages required for the LCD including a common voltage (VCOM), a gate high voltage signal (VGH), and a gate low voltage signal (VGL).
The gate drive sequentially transmits a scan pulse to the plurality of gate lines such that liquid crystal cells of the liquid crystal panel in line units are sequentially operated. The data drive transmits a pixel voltage signal to individual data lines whenever the scan pulse is applied to one of the gate lines. Therefore, the LCD controls the optical transmission rate by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell such that a desired image is displayed.
The gate drive includes a shift register for sequentially outputting the above-mentioned scan pulses. The shift register will hereinafter be described with reference to FIG. 1, which illustrates a related art shift register.
Referring to FIG. 1, the related art shift register includes N stages 100a˜100e dependently connected to each other and a single dummy stage 100f connected to the last of the N stages. In this case, individual stages 100a˜100e output scan pulses Vout1˜Voutn, respectively. The scan pulses Vout1˜Voutn are sequentially generated from the first stage 100a to the N-th stage 100e. The scan pulses Vout1˜Voutn generated from the stages 100a˜100e are sequentially applied to corresponding gate lines of the liquid crystal panel (not shown) such that the gate lines are sequentially scanned.
The stages 100a˜100e and the dummy stage 100f of the shift register receive a first source voltage VDD and a second source voltage VSS. The first source voltage VDD is a straight-polarity voltage and the second voltage VSS is a ground voltage. The stages 100a˜100f also receive two clock pulses from among first to fourth clock pulses CLK1˜CLK4 having a sequential phase difference with each other.
The first stage 100a receives a start pulse (SP) along with the first and second voltages VDD˜VSS and two clock pulses from among the first to fourth clock pulses CLK1˜CLK4.
Operations of the above-mentioned conventional shift register will hereinafter be described in detail.
Referring to FIG. 1, the start pulse (SP) generated from the timing controller (not shown) applied to the first stage 100a enables the first stage 100a. The enabled first stage 100a receives the first and second clock pulses CLK1 and CLK2 from the timing controller, outputs the first scan pulse Vout1, and transmits the first scan pulse Vout1 to the corresponding first gate line and to the second stage 100b to enable the second stage 100b. The second stage 100b answers the first scan pulse Vout1 when it is enabled.
The enabled second stage 100b receives the second and third clock pulses CLK2 and CLK3 from the timing controller, outputs the second scan pulse Vout2, and transmits the second scan pulse Vout2 to the corresponding second gate line, the third stage 100c, and to the first stage 100a. The second pulse Vout2 enables the third stage 100c which in turn answers the second scan pulse Vout2 when it is enabled. The second pulse Vout2 disable the first stage 100a such that the first stage transmits the second source voltage VSS, i.e. the ground voltage, to the first gate line to thereby deactivate the first gate line.
The enabled third stage 100c receives the third and fourth clock pulses CLK3 and CLK4 from the timing controller, outputs the third scan pulse Vout3, and transmits the third scan pulse Vout3 to the third gate line, to the fourth stage 100d, and to the second stage 100b. The fourth stage 100d answers the third scan pulse Vout3 when it is enabled and second stage 100b transmits the second source voltage VSS to the second gate line.
In a similar manner, the fourth to N-th scan pulses Vout4˜Voutn are sequentially transmitted to the fourth to N-th stages 100a˜100e, such that they are sequentially applied to the fourth to N-th gate lines. As a result, the first to N-th gate lines are sequentially scanned by the first to N-th scan pulses Vout1˜Voutn.
The dummy stage 100f answers the N-th scan pulse Voutn generated from the N-th stage 100e when it is enabled. Thereafter, the dummy stage 100f receives two clock pulses from the timing controller, and outputs the (N+1)-th scan pulse (Voutn+1). The (N+1)-th scan pulse (Voutn+1) is applied to the N-th stage 100e, such that the N-th stage 100e can provide the N-th gate line with the second source voltage VSS. In other words, the dummy stage 100f provides the (N+1)-th scan pulse (Voutn+1) to disable the N-th stage 100e such that the N-th output the second source voltage VSS. The dummy stage 100f does not transmit the (N+1)-th scan pulse (Voutn+1) to the gate line. Therefore, the number of all stages 100a˜100f including the above-mentioned dummy stage 100f is always higher than the number of the gate lines by one.
The above-mentioned related art shift register has the following problems.
FIG. 2 shows a normal scan pulse and a distorted scan pulse. It is desirable to have a large LCD area. However, larger LCD area requires longer gate lines. Unfortunately, longer gate lines are accompanied by higher resistances and capacitances.
As can be seen from FIG. 2, a scan pulse applied to the gate line may be distorted by the resistance and capacitance components. For example, a rising time of the scan pulse can increase such that a waveform of the scan pulse becomes distorted.
In the related art shift register, each of the stages 100a˜100e outputs a single scan pulse. Individual scan pulses generated from the stages 100a˜100e are simultaneously applied to the gate line, the next stage, and the previous stage which can result in a serious noise problem in the above-mentioned scan pulses. In other words, individual scan pulses generated from individual stages 100a˜100e are applied to not only the corresponding gate line, but also to other stages acting as resistance and capacitance components, such that distortion of the scan pulse is increased.
The distorted scan pulse has a rising time longer than that of a normal scan pulse, such that a valid charge time maintained at a target voltage is shortened. If the distorted scan pulse is applied to a gate electrode of the TFT, a turn-ON time of the TFT is also shortened such that a switching time during which the turned-on TFT switches a data voltage of the data line is shortened as well. In conclusion, the data voltage applied to the pixel electrode via drain and source terminals of the turned-ON TFT is distorted such that the pixel electrode cannot be sufficiently charged with the data voltage.
If the above-mentioned distorted scan pulses are applied to individual stages 100a˜100e, multiple output signals are generated from the stages 100a˜100e and are re-applied to the stages 100a˜100e. As a result, switching elements contained in individual stages 100a˜100e deteriorate such that unexpected erroneous operations may occur, and even worse, the switching elements may be greatly damaged.